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engineering specification type 21.3 qsxga monochrome tft/lcd module model name:IAQS80F document control number : oem i-980f-01 note:specification is subject to change without notice. consequently it is better to contact to international display technology before proceeding with the design of your product incorporating this module. sales support international display technology engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 1/33
i contents i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 physical interface 5.1 signal connectors 5.2 back light connector 5.3 interface signal description 5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver 5.4.2 back light control signal electrical characteristics 5.4.3 recommended guidelines for motherboard pcb design and cable selection 6.0 pixel format image 7.0 interface timings 7.1 timing characteristics 8.0 power consumption 9.0 power on/off sequence 10.0 mechanical characteristics 11.0 national test lab requirement engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 2/33
ii record of revision first edition for customer. based on internal spec. as of august 14,2002. all oem i-980f-01 october 8,2002 summary page document revision date engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 3/33
1.0 handling precautions if any signal or power line deviates from the power on/off sequence, it may cause shortening the life of the lcd module and/or damage the electrical components. also, hot plug-in operation may cause the similar damages as above. the lcd panel and the ccfl (cold cathode fluorescent lamp)s are made of glass and may break or crack if dropped on a hard surface. handling with care is necessary. the fluorescent lamp in the liquid crystal display (lcd) contains mercury. do not put it in trash that is disposed of in landfills. dispose of it as required by local ordinances or regulations. small amount of materials having no flammability grade is used in the lcd module. the lcd module should be applied to exemption conditions of the flammability requirements (4.4.3.3, en60950 or ul1950) in an end product. please handle with care when mounted in the system cover. mechanical damage for the lamp cable / lamp connector may cause safety problems. after installation of the tft module into an enclosure (monitor frame, for example), do not twist nor bent the tft module even momentary. at designing the enclosure, it should be taken into consideration that no bending/ twisting forces are applied to the tft module from out side. otherwise the tft module may be damaged. since cmos lsi is used in this module, take care of static electricity and insure human earth when handling. also, when removing a protection sheet from the module surface, please take some actions against static electricity, like earth band, ionic shower, etc. since front polarizer is easily damaged, pay attention not to scratch it. wipe off water drop immediately. long contact with water may cause discoloration or spots. when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. do not open nor modify the module assembly. prevent continuous 10 hours or over same pattern displaying, to avoid image sticking. the information contained herein may be changed without prior notice. it is therefore advisable to contact international display technology before proceeding with the design of equipment incorporationg this product. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by international display technology for any infringements of patents or other right of the third partied which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of international display technology or others. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 4/33
2.0 general description this specification applies to the type 21.3 monochrome tft/lcd module 'IAQS80F'. this module is designed for a module with neutral white (0.294, 0.309) and dicom gamma curve. the screen format and electrical interface are intended to support the qsxga (2560(h) x 2048(v)) screen with sensor area (176(h) x 16(v)) at the top of the screen. supported gray scales are native 8bit level (8-bit per tri-subpixels data driver). all input signals are lvds (low voltage differential signaling) interface compatible. this module contains an inverter card for backlight. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 5/33
2.1 characteristics 0 to +50 (note) -20 to +60 temperature range [degree c] operating storage (shipping) lvds (5pairs) x4 (rightx2, leftx2) electrical interface logic 8.1 typ., inverter 44 typ. power consumption [w] +12 +5/-8% (logic, inverter) input voltage [v] 25 typ. / 25 typ. optical rise time/fall time [msec] 600:1 typ. (in the dark room) contrast ratio 750 typ., 600 min. white luminance [cd/m 2 ] 8-bits per each subpixel supported grayscale dual domain ips, normally black display mode 459.8(w) x 375.3(h) x 48.5(d) typ. (w/ inverter) physical size [mm] 2,970 typ. weight [grams] tri-subpixels per one pixel, vertical stripe pixel arrangement 0.165 x 0.165 pixel pitch [mm] 29.04(h) x 2.64(v) sensor window [mm] 422.4(h) x 337.92(v) active area [mm] 176(h) x 16(v) top/right at landscape sensor window 2560(h) x 2048(v) pixels 54.09 screen diagonal [cm] specifications characteristics items note : max. operating temperature 50 deg.c in the spec means the temperature measured at the point of the front surface of the lcd glass cell. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 6/33
2.2 functional block diagram the following diagram shows the functional block diagram for the type 21.3 monochrome tft/lcd module. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 7/33
3.0 absolute maximum ratings absolute maximum ratings of the module is as follows; half sine wave (note 2) g ms 50 11 shock (note 2) g hz 1.5 10-200 vibration (note 1) %rh 95 5 hst storage relative humidity (note 1) deg.c +60 -20 tst storage temperature (note 1) %rh 80 8 hop operating relative humidity (note 1) deg.c +50 0 top operating temperature v +5.3 -1.0 blon backlight on signal v +5.3 -0.3 vdim brightness control v +17.6 -0.3 vbl backlight voltage v +17.6 -0.3 vin logic/lcd drive voltage conditions unit max min symbol item note 1 : maximum wet-bulb should be 39 degree c and no condensation. max. operating temperature 50 deg. c in the spec means the temperature measured for the point of the front surface of the lcd glass cell. note 2 : vibration specification - sine vibration:10-200-10hz, 1.5g, 30 min, x, y, z axis, each one time. shock specification - half sine wave:50g 11msec. -x+/-, -y+/-, -z+/- (total 6 directions), each one time shock. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 8/33
4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 degree c condition: 600 min. 750 typ. (center) white luminance (cd/m 2 ) + 0.030 0.309 white y + 0.030 0.294 white x white balance 50 max. 25 falling (ms) 50 max. 25 rising response time 400 min. 600 contrast ratio - - 85 85 vertical (upper) k 10 (lower) k:contrast ratio - - 85 85 horizontal (right) k 10 (left) viewing angle (degrees) note typ. specification conditions item engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 9/33
5.0 physical interface physical interface is described in accordance with the connectors on the lcd module. these connectors are capable of accommodating the following signals and will be the following components or idt approved types. 5.1 signal connectors all video signals are provided through the lvds cable from monitor card. these connectors are the input connector of video signals. the lvds signals, which are provided from monitor card, are described on the following table. signal connectors il-z-5s-s125c3 jae il-z-5pl-smty eedid interface j4 il-z-8s-s125c3 jae il-z-8pl-smty dc input j3 fi-x30h (for harness) fi-x30m ( for fpc ) jae fi-x30s-hf lvds input for right half screen j2 fi-x30h (for harness) fi-x30m ( for fpc ) jae fi-x30s-hf lvds input for left half screen j1 mating connector manufacturer type function connector lvds signals input pin assignment (j1 and j2) rboin3+ raoin3+ 30 gnd gnd 15 rboin3- raoin3- 29 rbein3+ raein3+ 14 gnd gnd 28 rbein3- raein3- 13 rboclkin+ raoclkin+ 27 gnd gnd 12 rboclkin- raoclkin- 26 rbeclkin+ raeclkin+ 11 gnd gnd 25 rbeclkin- raeclkin- 10 rboin2+ raoin2+ 24 gnd gnd 9 rboin2- raoin2- 23 rbein2+ raein2+ 8 gnd gnd 22 rbein2- raein2- 7 rboin1+ raoin1+ 21 gnd gnd 6 rboin1- raoin1- 20 rbein1+ raein1+ 5 gnd gnd 19 rbein1- raein1- 4 rboin0+ raoin0+ 18 gnd gnd 3 rboin0- raoin0- 17 rbein0+ raein0+ 2 gnd gnd 16 rbein0- raein0- 1 j2 j1 j2 j1 signal name pin # signal name pin # voltage levels of all input signals are lvds compatible in those connectors, j1 and j2. refer to "signal electrical characteristics for lvds". engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 10/33
logic dc input pin assignment (j3) vin 8 vin 7 vin 6 vin 5 return 4 return 3 return 2 return 1 signal name pin # eedid interface pin assignment (j4) gnd 5 sda 4 scl 3 reserved 2 eedid vcc 1 signal name pin # engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 11/33
5.2 back light connector backlight connector on inverter card phr-12 jst b12b-ph-sm3-tb input for backlight cn-1 mating connector manufacturer connector type function connector inverter input connector (cn-1) blon 12 vdim 11 gnd 10 gnd 9 gnd 8 gnd 7 gnd 6 vbl 5 vbl 4 vbl 3 vbl 2 vbl 1 signal name pin # engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 12/33
5.3 interface signal description signal description for j1, j2 ground gnd gnd positive lvds differential clock input (odd clock, lvds-rxo-clk) rboclkin+ raoclkin+ negative lvds differential clock input (odd clock, lvds-rxo-clk) rboclkin- raoclkin- positive lvds differential data input (odd data, lvds-rxo-3) rboin3+ raoin3+ negative lvds differential data input (odd data, lvds-rxo-3) rboin3- raoin3- positive lvds differential data input (odd data, lvds-rxo-2) rboin2+ raoin2+ negative lvds differential data input (odd data, lvds-rxo-2) rboin2- raoin2- positive lvds differential data input (odd data, lvds-rxo-1) rboin1+ raoin1+ negative lvds differential data input (odd data, lvds-rxo-1) rboin1- raoin1- positive lvds differential data input (odd data, lvds-rxo-0) rboin0+ raoin0+ negative lvds differential data input (odd data, lvds-rxo-0) rboin0- raoin0- positive lvds differential clock input (even clock, lvds-rxe-clk) rbeclkin+ raeclkin+ negative lvds differential clock input (even clock, lvds-rxe-clk) rbeclkin- raeclkin- positive lvds differential data input (even data, lvds-rxe-3) rbein3+ raein3+ negative lvds differential data input (even data, lvds-rxe-3) rbein3- raein3- positive lvds differential data input (even data, lvds-rxe-2) rbein2+ raein2+ negative lvds differential data input (even data, lvds-rxe-2) rbein2- raein2- positive lvds differential data input (even data, lvds-rxe-1) rbein1+ raein1+ negative lvds differential data input (even data, lvds-rxe-1) rbein1- raein1- positive lvds differential data input (even data, lvds-rxe-0) rbein0+ raein0+ negative lvds differential data input (even data, lvds-rxe-0) rbein0- raein0- j2 j1 description signal name note : 1. input signals of odd and even clock shall be the same timing. 2. the module uses a 100-ohm resister between positive and negative data lines of each receiver input. 3. even: first pixel, odd: second pixel 4. j1: stripe a (left half), j2: stripe b (right half) engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 13/33
signal description for j3 +12v power supply vin return to power supply (ground) return description signal name signal description for j4 reserved reserved eedid data sda eedid clock scl +3.3v power supply for eedid chip eedid vcc description signal name backlight power connector signal description for cn-1 on inverter card backlight on and off control signal. high (active): backlight on, low (inactive): backlight off blon dimming control voltage input. (0 - 3v) 0v: maximum brightness, 3v: minimum brightness vdim ground line for vbl, blon, vdim. to connect screw hole pattern through 0 ohm resister gnd power source line. 11.0 - 12.6 v vbl description signal name note : refer to the attached drawing for the connector position and pin no. 1 position. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 14/33
signal description horizontal sync: this signal is synchronized with dtclk. both active high/low signals are acceptable. hsync (h-s) vertical sync: this signal is synchronized with dtclk. both active high/low signals are acceptable. vsync (v-s) when the signal is high, the pixel data shall be valid to be displayed. +dsptmg (dsp) the signal is used to strobe the pixel +data and the +dsptmg (even/odd) data clock: the typical frequency is 74.0mhz. dtclk c sub pixel data: each c sub pixel's brightness data consists of these 8 bits pixel data. (even/odd) c sub pixel data 0 (lsb) +c0 (ec0/oc0) c sub pixel data 1 +c1 (ec1/oc1) c sub pixel data 2 +c2 (ec2/oc2) c sub pixel data 3 +c3 (ec3/oc3) c sub pixel data 4 +c4 (ec4/oc4) c sub pixel data 5 +c5 (ec5/oc5) c sub pixel data 6 +c6 (ec6/oc6) c sub pixel data 7 (msb) +c7 (ec7/oc7) b sub pixel data: each b sub pixel's brightness data consists of these 8 bits pixel data. (even/odd) b sub pixel data 0 (lsb) +b0 (eb0/ob0) b sub pixel data 1 +b1 (eb1/ob1) b sub pixel data 2 +b2 (eb2/ob2) b sub pixel data 3 +b3 (eb3/ob3) b sub pixel data 4 +b4 (eb4/ob4) b sub pixel data 5 +b5 (eb5/ob5) b sub pixel data 6 +b6 (eb6/ob6) b sub pixel data 7 (msb) +b7 (eb7/ob7) a sub pixel data: each a sub pixel's brightness data consists of these 8 bits pixel data. (even/odd) a sub pixel data 0 (lsb) +a0 (ea0/oa0) a sub pixel data 1 +a1 (ea1/oa1) a sub pixel data 2 +a2 (ea2/oa2) a sub pixel data 3 +a3 (ea3/oa3) a sub pixel data 4 +a4 (ea4/oa4) a sub pixel data 5 +a5 (ea5/oa5) a sub pixel data 6 +a6 (ea6/oa6) a sub pixel data 7 (msb) +a7 (ea7/oa7) description signal name note : output signals from any system shall be hi-z state when vin is off. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 15/33
lvds per each channel becomes as below. each channel has hsync (h-s), vsync (v-s) and dsptmg (dsp). 1 cycle 1 cycle rxein0+ rxoin0+ rxein2+ rxoin2+ rxein1+ rxoin1+ rxein3+ rxoin3+ ea3 oa3 ec5 oc5 eb4 ob4 ea1 oa1 ea2 oa2 ec4 oc4 eb3 ob3 ea0 oa0 eb2 ob2 dsp na ec3 oc3 na na ea7 oa7 v-s na ec2 oc2 ec1 oc1 ea6 oa6 h-s na eb7 ob7 ec0 oc0 ea5 oa5 ec7 oc7 eb6 ob6 eb1 ob1 ea4 oa4 ec6 oc6 eb5 ob5 eb0 ob0 ea3 oa3 ec5 oc5 eb4 ob4 ea1 oa1 ea2 oa2 ec4 oc4 eb3 ob3 ea0 oa0 eb2 ob2 dsp na ec3 oc3 na na rxein0- rxoin0- rxeclkin+ rxoclkin+ rxeclkin- rxoclkin- rxein2- rxoin2- rxein1- rxoin1- rxein3- rxoin3- note : a/b/c data 7: msb, a/b/c data 0: lsb, dsp = dsptmg, v-s = vsync, h-s = hsync, x: a (stripe a)or b(stripe b) engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 16/33
5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver each signal characteristics are as follows; electrical characteristics vth-vtl=200mv [mv] +50 -50 vcm common mode voltage offset vth-vtl=200mv [v] | vid | 2.0 - 2 | vid | 0.825+ 2 vic common mode input voltage [mv] 600 100 |vid| magnitude differential input voltage vcm=+1.2v [mv] -100 vtl differential input low threshold vcm=+1.2v [mv] +100 vth differential input high threshold conditions unit max min symbol parameter note: input signals shall be low or hi-z state when vdd is off. all electrical characteristics for lvds signal are defined and shall be measured at the interface connector of lcd (see figure measurement system). IAQS80F has a 100-ohm resister between poritive and negative lines of each lvds signal input. voltage definitions engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 17/33
measurement system lvds receiver ac characteristics [ps/clk] 20 tcjavg cycle modulation rate (note 4) [ps] +150 -150 tccj cycle-to-cycle jitter (note 3) [ps] 500 thd data hold time (note 2) fc = 74.0[mhz], tccj < 50[ps], vth-vtl=200[mv], vcm=1.2[v], vcm=0[v] [ps] 500 tsu data setup time (note 2) [ns] 13.5 tc cycle time [mhz] 74.0 fc clock frequency conditions unit max typ min symbol parameter note : 1. all values are at vin=12.0[v], ta=25[c deg.]. 2. see figure "lvds format" and "detail timing definition" for definition. 3. jitter is the magnitude of the change in input clock period. 4. this specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. figure "cycle modulation rate" illustrates a case against this requirement. this specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 18/33
detail timing definition note : tsu and thd are internal data sampling window of receiver. trskm is the system skew margin; i.e., the sum of cable skew, source clock jitter, and other inter-symbol interference, shall be less than trskm . engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 19/33
cycle modulation rate engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 20/33
lvds receiver internal circuit below figure shows the internal block diagram of the lvds receiver. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 21/33
5.4.2 back light control signal electrical characteristics inverter input signal electrical characteristics [ma] 1.0 - -1.0 current 0[v] : brightness max 3[v] : brightness min [v] 3.0 - 0.0 input voltage range vdim [ma] 1.0 - -1.0 current [v] 0.8 0.0 -0.3 low level voltage [v] 5.0 3.0 2.0 high level voltage blon note unit max typ min description name the following chart is the vdim versus dimming range for your reference. IAQS80F v_dim vs dimming characteristics 0% 20% 40% 60% 80% 100% 120% 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v_dim(v) luminance ratio(%) engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 22/33
5.4.3 recommended guidelines for motherboard pcb design and cable selection following the suggestions below will help to achieve optimal results. use controlled impedance media for lvds signals. they should have a matched differential impedance of 100ohm. match electrical lengths between traces to minimize signal skew. isolate ttl signals from lvds signals. for cables, twisted pair, twinax, or flex circuit with close coupled differential traces are recommended. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 23/33
6.0 pixel format image following figure shows the relationship between the input signals and the lcd pixel format image. IAQS80F has 4 sets of lvds interface and they are bundled to two channels. the screen is divided into two vertical stripe screens (stripe a and stripe b) and each channel controls one of the half-size screens (1280 pixels x 2064 lines included sensor lines). channel a and channel b are corresponding to stripe a and stripe b individually. channel a includes 2 sets of lvds (lvds-a-e and lvds-a-o) and the other channels are also the same manner. screen format engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 24/33
7.0 interface timings 7.1 timing characteristics the tft screen is divided to 2 vertically and each vertical stripe screen has the interface channel to be input video timing. so the number of channel is 2. timings among channels should be synchronized with each other (frame lock). ==> same clock source, same v/h-sync timing, same video timing the interface of channel is lvds (dual pixel inputs). the sensor area exists the top of screen. and it is recommended for these areas to be filled with the same image of 1st line of actual displayed image except for calibration time. vertical stripe screen a b x frame locked 1280x 2064 @ 50hz/frame 104 khz/h 148 mhz/dot x 2 t-con 2 vertical stripe screen with sensor area on top of screen lvds x 2048 1280 1280 2560 a b 16 2064 sensor area display area engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 25/33
following is the video timing per channel to be converted to/from lvds interface. th tha thb thf tck 0 1 2 3 n-2 n-1 thd video signal, hsync and dot clock dsptmg video(even) video(odd) dot clock hsync tv tvb tvf tva 0k-1 vsync, hsync and display timing vsync hsync dsptmg m-1 0 note : 1. the sensor lines exist on top of screen, and it is recommended for this area to be filled with the same image of 1st line of actual displayed image except for calibration time. and also these lines need dsptmg. 2. even dot for 1st dot, odd dot for 2nd dot. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 26/33
timing characteristics [pixels] - 1280 - n display pixels +dsptmg [tck] - 640 - thd display clocks +dsptmg [tck] 383 72 40 thf+tha+thb h-blank +h-sync [tck] 8 4 thb h-back porch +h-sync [tck] 8 4 tha h-active level +h-sync [tck] 56 32 thf h-front porch +h-sync [tck] 1023 712 680 th cycle +h-sync [us] 9.62 th h-scan rate +h-sync [khz] 103.9 1/th h-scan rate +h-sync [lines] - 2048 - m normal lines / frame +dsptmg [lines] - 16 - k sensor lines / frame +dsptmg [lines] - 2064 - k+m display lines / frame +dsptmg [lines] 255 12 8 tvf+tva+tvb v-blank +v-sync [lines] 127 8 6 tvb v-back porch +v-sync [lines] 1 1 tva v-active level +v-sync [lines] 3 1 tvf v-front porch +v-sync [lines] 2303 2076 2072 tv total line +v-sync [ms] 20.00 tv frame period +v-sync [hz] 50.06 1/tv refresh rate +v-sync [ns] 14.08 13.51 13.16 tck dot clock period dtclk [mhz] 76 74 71 fdck dot clock freq. dtclk unit max. typ. min. symbol item signal note : 1. h/v sync polarity will be acceptable both positive and negative. dsptmg (data enable) should be active high. 2. vsync should not be changed at hsync leading edge (+/- 6 [tck]). 3. even dot clock and odd dot clock in each channel should have completely the same clock source. the skew should be within +/- 1.5[ns]. 4. all timing among channels should be synchronized (vsync, hsync, dsptmg, video and clocks) and the skew of vsync etc. among channels should be within +/- 1 tck. 5. all channels should be activated any time after power on (because it does not have auto refresh protection). engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 27/33
8.0 power consumption [mvp-p] 100 allowable backlight drive ripple noise vbl ns [mvp-p] 100 allowable backlight drive ripple voltage vbl rp vbl=12.0[v] stand-by [w] 0.5 vbl=12.0[v] min. brightness. [w] 10.0 8.0 vbl=12.0[v] max. brightness. [w] 50.0 44.0 backlight power consumption (note 4) pbl 30 minutes after power on [a] 4.2 3.7 3.0 2 minutes after power on [a] 4.7 4.0 3.2 vbl current ibl [v] 12.6 12.0 11.0 backlight power voltage vbl [mvp-p] 100 allowable logic/lcd drive ripple noise vin ns [mvp-p] 100 allowable logic/lcd drive ripple voltage vin rp vin=11.0 to 12.6[v] (note 2) [w] 18.3 vin power (2) pin(2) vin=12.0[v] (note 3) [w] 8.1 vin power (1) pin(1) vin=12.0[v] (note 2) [a] 1.0 0.7 vin current (2) iin(2) vin=11.0 to 12.6[v] (note 1) [a] 1.7 vin current (1) iin(1) [v] 12.6 12.0 11.0 logic/lcd drive voltage vin condition units max. typ. min. parameter symbol note : 1. horizontally-sub-pixel/vertically-double-pixel checker 2. all white (l255) screen 3. horizontal gray bar(left=black, right=white) 4. measurement after ccfl luminance saturation. (minimum 60 minutes.) engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 28/33
9.0 power on/off sequence vin power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vin is off. engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 29/33
10.0 mechanical characteristics engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 30/33
engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 31/33
active area / sensor area engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 32/33
11.0 national test lab requirement the display module is authorized to apply the ul recognized mark. conditions of acceptability conditions of acceptability - when installed in the end-product, consideration shall be given to the following; 1. this component has been judged on the basis of the required spacing in the standard for safety of information technology equipment, csa/ul 60950, third edition, dated december 1, 2000, sub-clause 2.10, which would cover the component itself if submitted for listing. 2. the inverter output circuit is limited current circuits. 3. the unit is intended to be supplied by selv and limited power source. also separated form electrical ports, which may produce high temperature that could cause ignition by as least 13mm of air or by a solid barrier of material of v-1 minimum. 4. the terminals and connectors are suitable for factory wiring only. 5. a suitable fire/electrical enclosure shall be considered at end-product evaluation. ****** end of page ****** engineering specification (c) copyright international display technology 2002 all rights reserved. october 8,2002 oem i-980f-01 33/33

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